The present invention relates to an integrated circuit arrangement comprising at least one digital-analogue converter.
1. Field of the Invention
In particular, the present invention relates to such arrangement comprising at least one digital-analogue converter with a multitude of current-source transistors arranged parallel to each other for providing current components that in each case are predetermined in a fixed manner and are used to form an analogue current signal, wherein control inputs of the current-source transistors can be subjected to a shared adjustment potential by way of an adjustment potential line, which adjustment potential defines the individual current components, and comprising an adjustment circuit for providing the adjustment potential at the adjustment potential line.
2. Description of the Prior Art
Such circuit arrangements and in particular the architecture of the digital-analogue converter or converters implemented therein, hereinafter abbreviated to “DAC”, are known from prior art.
FIG. 1 shows some components of a conventional digital-analogue converter that are essential to understanding the present invention.
The part of the DAC shown in FIG. 1 comprises a multitude (in the present example 8) of FETs N1-N8 (“current-source transistors”) arranged in parallel. During operation of the DAC the transistors N1-N8 are used to provide current components I1-I8 that are predetermined in a fixed manner and are used to form an analogue current signal. By means of a part of the DAC that is not shown in FIG. 1, these current components I1-I8, depending on the state of an input digital signal, contribute to an analogue current signal that is obtained by addition of the single current components. In this arrangement, switching a particular current component on and off can take place in a manner that is known per se by way of a switching transistor arranged in series with the respective current-source transistor. The current components actually selected by the digital signal contribute to the analogue output signal of the DAC, either directly by outputting a current signal, or indirectly by outputting a voltage signal that can, for example, be obtained in that the current signal is fed by way of a resistor element.
As shown in FIG. 1, the control inputs (presently gate connections) of the transistors N1-N8 are connected to each other and by way of a line connection, which hereinafter is designated an “adjustment potential line”, are connected to the gate connection of a FET Nbias, which is switched in a way that is known per se as a current adjustment transistor, through which a predetermined reference current Ibias flows.
The arrangement shown thus implements a current mirror that mirrors the reference current Ibias that flows through the reference transistor Nbias to the multitude of current paths of the current source transistors N1-N8. The gate potential that arises based on the reference current Ibias at the transistor Nbias determines the values of the individual current components I1-I8 that contribute to the DAC output signal.
Any interference in the area of generating and transmitting this adjustment potential leads to corresponding interference, possibly even magnified, of the current components I1-I8 that in an ideal case are predetermined in a fixed manner. In this regard, for example, noise, e.g. thermal noise, in the reference current Ibias has a very disadvantageous effect on the current components I1-I8.